The ADC ADC data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital con- verter 8-channel multiplexer and. ADC ADC – 8-bit Microprocessor Compatible A/D Converters With 8- Channel Multiplexer, Details, datasheet, quote on part number: ADC The ADC/ADC Data Acquisition Devices (DAD) implement on a single chip most the elements of the stan- dard data acquisition system. They contain.
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The source resistance must be below 10kohms for operation below kHz and below 5kohms for operation around 1.
The voltage level that, when received as an input, will output “” to the FPGA. The start signal should conform to the same range as all other control signals.
Analog to Digital Converter – ADC/ADC
This means that an entire conversion takes at least 64 clock cycles. It is recomended that the source resistance not exceed 5kohms datahseet operation at 1. Clock The clock signal is required to cycle through the comparator stages to do the conversion. The following control signals are used to control the conversion.
Source code The source code consists of a few of files. Once loaded the multiplexer sends the appropriate channel to the converter on the chip.
The signal can be tie to the ALE signal when the clock frequency is below kHz. Address Lines Because the chip has an 8 channel multiplexer there are three address select datasueet Be sure to consult the manufactures data-sheets for other chips. Top rail of Reference voltage. It can be tied to the Start line if the clock is operated under kHz. In this implementation the OE signal is pulsed high one clock cycle after the EOC signal goes high and remains high until the data is safely stored into the desired register in the FPGA.
The maximum frequence of the clock is 1. Signal from the ADC. This means that in order to get it to work, there is a total of seven control signals that must be sent from the FPGA.
It is a control signal avc0809 the FPGA, which tells the converter when to start a conversion. The minimum pulse width is ns.
As with all control signals it is required to have an input value of Vcc – 1. Control signal from FPGA.
ADC Datasheet(PDF) – National Semiconductor (TI)
Users can look for a rising edge transition. This means it must remain stable for up to 72 clock cycles. Adc809 to 72 if the start signal is received in the middle of an 8 clock cycle period. Table 2 provides a summary of all of the input and output to the chip.
Like the ALE pulse the minimum pulse width is ns. Begin by downloading the files into your desired destination directory and then compile axc0809 in this order. It is a pulse of at least ns in width. The ADC stores the data in a tri-state output latch until the next conversion is started, but the data is only output when enabled.
It is the Second bit of the select lines.
On the rising edge of the pulse the internal registers are cleared and on the falling edge of the pulse the conversion is initiated. It is the MSB of the select lines. If Vcc and daatsheet are used as reference voltages, they should be isolated by decoupling with a 1 microF capacitor. The source code provided was used to control an ADC where only 4 inputs were used, therefore, ADD C is tied to ground and so are the unused inputs.
It is the LSB of the select lines. It goes low when a conversion is started and high at the end of a conversion. All control signals should have a high voltage from Vcc – 1. Bottom rail of Reference voltage.
There are 8, 8 clock cycle periods required in order to complete an entire conversion. That is because ADCs require clocking and can contain control logic including comparators and registers. Note that it can take up to 2. C is the most significant bit and A is the least. The OE signal datqsheet conform to the same range as all the other control signals.
Unfortunately you cannot just hook up analog inputs to an ADC and expect to get digital outputs from the chip without adding control signals. The maximum clock frequency is affected by the source impedance of the analog inputs. The clock should conform to the same range as all other control signals. The source must remain stable while it is being sampled and should contain little noise. This is an address select line for the multiplexer.
The ALE should be pulsed for at least ns in order for the addresses to get loaded properly. At clock speeds greater than that the user must make certain that enough time has passed since the ALE signal was pulsed so that the correct address is loaded into the multiplexer before a conversion begins. Start The purpose asc0809 the start signal is two fold. Modification to the source code are required to use more than just four channels. All of the signals are explained below.
A, B, and C. The other files are enabled register, a register, and a multiplexer.